SR flip-flop is one of the most common types of flip-flop. SR stands for Set Reset.
Figure(a) shows the graphic symbol of SR flip-flop. The flip-flop has three inputs S (set), R, (reset) and C (clock). The set S and reset R specify the internal logic states of SR flip-flop.
The arrow head symbol in front of clock C designates the dynamic input. That is the flip-flop responds to a positive transition (from 0 to 1) of the input clock signal.
The Outputs are denoted by Q. The SR flip-flop can also have a complimentary output represented by a small circle at the other output terminal.
SR flip-flop is also known as SR latch. It can also be called RS flip-flop.
Following figure(b) is logic diagram of a clocked SR flip-flop. It consists of two NOR flip-flops and two NAND flip-flops. A typical SR flip-flop can be built with cross coupled NOR gates. The outputs of the AND gates are 0 as long as the clock pulse is irrespective of the inputs S and R.
Following table is the characteristic table for SR flip-flop. When the input S is 1 and R is 0, output Q’ becomes 0 and Q becomes 1.
Figure(c): Characteristic table